// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  cfg_fte_reg_offset_field.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1
// Date          :  2013/3/10
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2 
// History       :  xxx 2018/03/16 17:23:29 Create file
// ******************************************************************************

#ifndef __CFG_FTE_REG_OFFSET_FIELD_H__
#define __CFG_FTE_REG_OFFSET_FIELD_H__

#define CFG_FTE_FTE_ICG_EN_LEN    1
#define CFG_FTE_FTE_ICG_EN_OFFSET 0

#define CFG_FTE_FTE_AW_INTERVAL_CYCLE_LEN    16
#define CFG_FTE_FTE_AW_INTERVAL_CYCLE_OFFSET 16
#define CFG_FTE_FTE_AR_INTERVAL_CYCLE_LEN    16
#define CFG_FTE_FTE_AR_INTERVAL_CYCLE_OFFSET 0

#define CFG_FTE_FTE_NS_CFG_ENABLE_LEN    1
#define CFG_FTE_FTE_NS_CFG_ENABLE_OFFSET 0

#define CFG_FTE_POE_512_BIT_MODE_LEN    1
#define CFG_FTE_POE_512_BIT_MODE_OFFSET 11
#define CFG_FTE_POE_TEST_MODE_LEN       1
#define CFG_FTE_POE_TEST_MODE_OFFSET    10
#define CFG_FTE_RW_MODE_LEN             2
#define CFG_FTE_RW_MODE_OFFSET          8
#define CFG_FTE_CMD_ENDLESS_LEN         1
#define CFG_FTE_CMD_ENDLESS_OFFSET      7
#define CFG_FTE_ADDR_INCREMENT_LEN      4
#define CFG_FTE_ADDR_INCREMENT_OFFSET   3
#define CFG_FTE_ADDR_INCR_MODE_LEN      1
#define CFG_FTE_ADDR_INCR_MODE_OFFSET   2
#define CFG_FTE_ADDR_COMMON_MODE_LEN    2
#define CFG_FTE_ADDR_COMMON_MODE_OFFSET 0

#define CFG_FTE_FTE_CMD_NUM_LEN    32
#define CFG_FTE_FTE_CMD_NUM_OFFSET 0

#define CFG_FTE_WSTROBE_MODE_LEN    1
#define CFG_FTE_WSTROBE_MODE_OFFSET 10
#define CFG_FTE_WDATA_MODE_LEN      2
#define CFG_FTE_WDATA_MODE_OFFSET   8
#define CFG_FTE_WDATA_PYLOD_LEN     8
#define CFG_FTE_WDATA_PYLOD_OFFSET  0

#define CFG_FTE_FTE_ADDR_EN_L_LEN    32
#define CFG_FTE_FTE_ADDR_EN_L_OFFSET 0

#define CFG_FTE_FTE_ADDR_EN_H_LEN    32
#define CFG_FTE_FTE_ADDR_EN_H_OFFSET 0

#define CFG_FTE_FTE_ADDR_L_LEN    32
#define CFG_FTE_FTE_ADDR_L_OFFSET 0

#define CFG_FTE_FTE_ADDR_H_LEN    32
#define CFG_FTE_FTE_ADDR_H_OFFSET 0

#define CFG_FTE_AW_ID_MODE_LEN       1
#define CFG_FTE_AW_ID_MODE_OFFSET    16
#define CFG_FTE_FTE_AW_ID_MAX_LEN    8
#define CFG_FTE_FTE_AW_ID_MAX_OFFSET 8
#define CFG_FTE_FTE_AW_ID_LEN        8
#define CFG_FTE_FTE_AW_ID_OFFSET     0

#define CFG_FTE_AW_LOCK_LEN     1
#define CFG_FTE_AW_LOCK_OFFSET  28
#define CFG_FTE_AW_QOS_LEN      4
#define CFG_FTE_AW_QOS_OFFSET   24
#define CFG_FTE_AW_SIZE_LEN     3
#define CFG_FTE_AW_SIZE_OFFSET  21
#define CFG_FTE_AW_LEN_LEN      6
#define CFG_FTE_AW_LEN_OFFSET   15
#define CFG_FTE_AW_PROT_LEN     3
#define CFG_FTE_AW_PROT_OFFSET  12
#define CFG_FTE_AW_CACHE_LEN    4
#define CFG_FTE_AW_CACHE_OFFSET 8

#define CFG_FTE_FTE_AW_USER0_LEN    32
#define CFG_FTE_FTE_AW_USER0_OFFSET 0

#define CFG_FTE_FTE_AW_USER1_LEN    32
#define CFG_FTE_FTE_AW_USER1_OFFSET 0

#define CFG_FTE_FTE_AW_USER2_LEN    32
#define CFG_FTE_FTE_AW_USER2_OFFSET 0

#define CFG_FTE_AR_ID_MODE_LEN       1
#define CFG_FTE_AR_ID_MODE_OFFSET    16
#define CFG_FTE_FTE_AR_ID_MAX_LEN    8
#define CFG_FTE_FTE_AR_ID_MAX_OFFSET 8
#define CFG_FTE_FTE_AR_ID_LEN        8
#define CFG_FTE_FTE_AR_ID_OFFSET     0

#define CFG_FTE_AR_LOCK_LEN     1
#define CFG_FTE_AR_LOCK_OFFSET  28
#define CFG_FTE_AR_QOS_LEN      4
#define CFG_FTE_AR_QOS_OFFSET   24
#define CFG_FTE_AR_SIZE_LEN     3
#define CFG_FTE_AR_SIZE_OFFSET  21
#define CFG_FTE_AR_LEN_LEN      6
#define CFG_FTE_AR_LEN_OFFSET   15
#define CFG_FTE_AR_PROT_LEN     3
#define CFG_FTE_AR_PROT_OFFSET  12
#define CFG_FTE_AR_CACHE_LEN    4
#define CFG_FTE_AR_CACHE_OFFSET 8

#define CFG_FTE_FTE_AR_USER0_LEN    32
#define CFG_FTE_FTE_AR_USER0_OFFSET 0

#define CFG_FTE_FTE_AR_USER1_LEN    32
#define CFG_FTE_FTE_AR_USER1_OFFSET 0

#define CFG_FTE_FTE_AR_USER2_LEN    32
#define CFG_FTE_FTE_AR_USER2_OFFSET 0

#define CFG_FTE_FTE_TEST_START_LEN    1
#define CFG_FTE_FTE_TEST_START_OFFSET 0

#define CFG_FTE_FTE_MAGIC_WORD_LEN    32
#define CFG_FTE_FTE_MAGIC_WORD_OFFSET 0

#define CFG_FTE_FTE_ECO_CFG0_LEN    32
#define CFG_FTE_FTE_ECO_CFG0_OFFSET 0

#define CFG_FTE_FTE_ECO_CFG1_LEN    32
#define CFG_FTE_FTE_ECO_CFG1_OFFSET 0

#define CFG_FTE_FTE_ECO_CFG2_LEN    32
#define CFG_FTE_FTE_ECO_CFG2_OFFSET 0

#define CFG_FTE_FTE_ECO_CFG3_LEN    32
#define CFG_FTE_FTE_ECO_CFG3_OFFSET 0

#define CFG_FTE_FTE_VERSION_LEN    32
#define CFG_FTE_FTE_VERSION_OFFSET 0



#define CFG_FTE_FTE_BUSY_ST_LEN    1
#define CFG_FTE_FTE_BUSY_ST_OFFSET 0

#define CFG_FTE_ERR_RID_LEN            8
#define CFG_FTE_ERR_RID_OFFSET         10
#define CFG_FTE_DATA_ERR_FLAG_LEN      1
#define CFG_FTE_DATA_ERR_FLAG_OFFSET   7
#define CFG_FTE_RERR_FLAG_LEN          1
#define CFG_FTE_RERR_FLAG_OFFSET       6
#define CFG_FTE_RRESP_ERR_LEN          2
#define CFG_FTE_RRESP_ERR_OFFSET       4
#define CFG_FTE_WERR_FLAG_LEN          1
#define CFG_FTE_WERR_FLAG_OFFSET       3
#define CFG_FTE_WRESP_ERR_LEN          2
#define CFG_FTE_WRESP_ERR_OFFSET       1
#define CFG_FTE_FTE_TEST_FINISH_LEN    1
#define CFG_FTE_FTE_TEST_FINISH_OFFSET 0

#define CFG_FTE_FTE_AW_UNFINISH_LEN    8
#define CFG_FTE_FTE_AW_UNFINISH_OFFSET 8
#define CFG_FTE_FTE_AR_UNFINISH_LEN    8
#define CFG_FTE_FTE_AR_UNFINISH_OFFSET 0

#define CFG_FTE_FTE_AW_CNUM_L_LEN    32
#define CFG_FTE_FTE_AW_CNUM_L_OFFSET 0

#define CFG_FTE_FTE_AW_CNUM_H_LEN    32
#define CFG_FTE_FTE_AW_CNUM_H_OFFSET 0

#define CFG_FTE_FTE_AW_RNUM_L_LEN    32
#define CFG_FTE_FTE_AW_RNUM_L_OFFSET 0

#define CFG_FTE_FTE_AW_RNUM_H_LEN    32
#define CFG_FTE_FTE_AW_RNUM_H_OFFSET 0

#define CFG_FTE_FTE_AR_CNUM_L_LEN    32
#define CFG_FTE_FTE_AR_CNUM_L_OFFSET 0

#define CFG_FTE_FTE_AR_CNUM_H_LEN    32
#define CFG_FTE_FTE_AR_CNUM_H_OFFSET 0

#define CFG_FTE_FTE_AR_RNUM_L_LEN    32
#define CFG_FTE_FTE_AR_RNUM_L_OFFSET 0

#define CFG_FTE_FTE_AR_RNUM_H_LEN    32
#define CFG_FTE_FTE_AR_RNUM_H_OFFSET 0

#define CFG_FTE_ERR_ADDR_L_LEN    32
#define CFG_FTE_ERR_ADDR_L_OFFSET 0

#define CFG_FTE_ERR_ADDR_H_LEN    32
#define CFG_FTE_ERR_ADDR_H_OFFSET 0

#define CFG_FTE_ERR_DATA_0_LEN    32
#define CFG_FTE_ERR_DATA_0_OFFSET 0

#define CFG_FTE_ERR_DATA_L_LEN    32
#define CFG_FTE_ERR_DATA_L_OFFSET 0

#define CFG_FTE_ERR_DATA_2_LEN    32
#define CFG_FTE_ERR_DATA_2_OFFSET 0

#define CFG_FTE_ERR_DATA_3_LEN    32
#define CFG_FTE_ERR_DATA_3_OFFSET 0

#define CFG_FTE_ERR_DATA_4_LEN    32
#define CFG_FTE_ERR_DATA_4_OFFSET 0

#define CFG_FTE_ERR_DATA_5_LEN    32
#define CFG_FTE_ERR_DATA_5_OFFSET 0

#define CFG_FTE_ERR_DATA_6_LEN    32
#define CFG_FTE_ERR_DATA_6_OFFSET 0

#define CFG_FTE_ERR_DATA_7_LEN    32
#define CFG_FTE_ERR_DATA_7_OFFSET 0

#define CFG_FTE_FTE_LAST_RDATA0_LEN    32
#define CFG_FTE_FTE_LAST_RDATA0_OFFSET 0

#define CFG_FTE_FTE_LAST_RDATA1_LEN    32
#define CFG_FTE_FTE_LAST_RDATA1_OFFSET 0

#define CFG_FTE_FTE_LAST_RDATA2_LEN    32
#define CFG_FTE_FTE_LAST_RDATA2_OFFSET 0

#define CFG_FTE_FTE_LAST_RDATA3_LEN    32
#define CFG_FTE_FTE_LAST_RDATA3_OFFSET 0

#define CFG_FTE_FTE_LAST_RDATA4_LEN    32
#define CFG_FTE_FTE_LAST_RDATA4_OFFSET 0

#define CFG_FTE_FTE_LAST_RDATA5_LEN    32
#define CFG_FTE_FTE_LAST_RDATA5_OFFSET 0

#define CFG_FTE_FTE_LAST_RDATA6_LEN    32
#define CFG_FTE_FTE_LAST_RDATA6_OFFSET 0

#define CFG_FTE_FTE_LAST_RDATA7_LEN    32
#define CFG_FTE_FTE_LAST_RDATA7_OFFSET 0

#define CFG_FTE_FTE_AW_DAVG_L_LEN    32
#define CFG_FTE_FTE_AW_DAVG_L_OFFSET 0

#define CFG_FTE_FTE_AW_DAVG_H_LEN    32
#define CFG_FTE_FTE_AW_DAVG_H_OFFSET 0

#define CFG_FTE_FTE_AW_DMAX_L_LEN    32
#define CFG_FTE_FTE_AW_DMAX_L_OFFSET 0

#define CFG_FTE_FTE_AW_DMAX_H_LEN    32
#define CFG_FTE_FTE_AW_DMAX_H_OFFSET 0

#define CFG_FTE_FTE_AR_DAVG_L_LEN    32
#define CFG_FTE_FTE_AR_DAVG_L_OFFSET 0

#define CFG_FTE_FTE_AR_DAVG_H_LEN    32
#define CFG_FTE_FTE_AR_DAVG_H_OFFSET 0

#define CFG_FTE_FTE_AR_DMAX_L_LEN    32
#define CFG_FTE_FTE_AR_DMAX_L_OFFSET 0

#define CFG_FTE_FTE_AR_DMAX_H_LEN    32
#define CFG_FTE_FTE_AR_DMAX_H_OFFSET 0

#endif // __CFG_FTE_REG_OFFSET_FIELD_H__
